The present disclosure relates generally to integrated circuit design, and more specifically, to sharing global route topologies in global and detailed routing.
The design of the layout of an integrated circuit typically includes both global routing and detailed routing. Global routing is used to find a rough path for each net by defining routing regions and generating a tentative route that specifies a set of routing regions traversed for each net being routed. During the global routing process, each net is assigned to a set of routing regions, however the actual layout of wires is not specified. The actual layout of wires used by the nets is typically specified during detailed routing. During detailed routing, for each routing region, each net that passing through that region is assigned particular routing tracks and the layout of the wires is fixed.
Two strategies are often applied in state-of-the-art global and detail routing tools in order to revise and/or to repair decisions made upstream in the flow: rip-up-and-reroute; and incremental updates. The initial global routing solution generated by the global routing process can create congestion and alternate global routing topologies are often searched for a set of nets in order to eliminate congestion. Even if global routing is successful, detailed routing is often not able to close all connections, and alternative detailed routing paths are searched in order to find a connected detailed routing solution. It can be time-consuming and not always possible to find alternate routes (global, detail) using the rip-up-and-reroute strategy and/or the incremental update strategy.